From afbbf2c8f638ba406b6f002fffe73f5761a5b658 Mon Sep 17 00:00:00 2001 From: Julien Grall Date: Wed, 18 Nov 2015 17:27:56 +0000 Subject: [PATCH] xen/arm: vgic-v2: Implement correctly ICFGR{0, 1} read-only Each ITARGETSR register is 4-bytes wide and the offset is in bytes. The current implementation is computing the offset of ICFGR1 and ICFG2 wrongly result to emulate only the first 2 byte of the ICFGR range read-only. The rest will be treated as read-write. For convenience introduce ITARGETSR1 and ITARGETSR2. Signed-off-by: Julien Grall Acked-by: Ian Campbell [ ijc -- typoes in commit message ] --- xen/arch/arm/vgic-v2.c | 6 ++++-- xen/include/asm-arm/gic.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index c94f0f37ea..4fb954be18 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -507,10 +507,12 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info, case GICD_ICFGR: /* SGIs */ goto write_ignore_32; - case GICD_ICFGR + 1: /* PPIs */ + + case GICD_ICFGR1: /* It is implementation defined if these are writeable. We chose not */ goto write_ignore_32; - case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */ + + case GICD_ICFGR2 ... GICD_ICFGRN: /* SPIs */ if ( dabt.size != DABT_WORD ) goto bad_width; rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD); if ( rank == NULL) goto write_ignore; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 3064d1c00f..42a2eeccb0 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -46,6 +46,8 @@ #define GICD_ITARGETSR8 (0x820) #define GICD_ITARGETSRN (0xBF8) #define GICD_ICFGR (0xC00) +#define GICD_ICFGR1 (0xC04) +#define GICD_ICFGR2 (0xC08) #define GICD_ICFGRN (0xCFC) #define GICD_NSACR (0xE00) #define GICD_NSACRN (0xEFC) -- 2.30.2